The trend in the semiconductor industry today is the production of ever increasingly more capable semiconductor components, while decreasing component size and increasing total semiconductor package density. With the need to achieve ever smaller package sizes and handle additional high-speed input/output signals, new wire-bonding and pad-layout configurations are sought.
Conventional wire-bonding methods, as illustrated in FIG. 1, are unable to fully accommodate high-speed differential pairs of signals which optimally require two wire bonds (e.g., a pair of copper or gold interconnectors) to be physically bonded as close to each other as possible in order to achieve maximum coupling effects and as high a common-mode rejection ratio (CMRR) as possible within the electronics device. FIG. 1 illustrates a conventional single row of wire-bond pad arrays 102, most often seen in typical integrated circuit (IC) package manufacturing processes. Note that as illustrated in FIG. 1, there are only two rows of in-line conventional bonding pads 102, one on each side of the silicon die 104 (e.g., semiconductor chip).
In order to meet the signal transmission requirements of high speed signals (e.g., high-speed differential pairs) received by input-output (I/O) interfaces seen in, for example, DDR-III memory modules and PCI-E electrical interfaces, as well as an increased quantity of input/output signals, conventional bonding methods would require longer rows of bond pads and hence a larger die size to accommodate the growing numbers of bonding pads (to accommodate the increased quantity of I/O signals). In other words, there is fixed quantity of wires that can be bonded to a silicon die of a given size without enlarging the silicon die size. Furthermore, the close coupling between adjacent wire bonds is not adequate to meet the tightening production parameters using current methods of wire-bonding, as illustrated in FIG. 1.